"I have a mind like a steel... uh... thingy." Patrick Logan's weblog.

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Monday, August 13, 2007

The Multicore Wall

An anonymous comment to my most recent thingy mentioning Erlang says...

Not everyone is buying the Erlang hype.
And the comment links to Steve Dekorte's recent post on "the multi-core wall".

Fair cautions about "Erlang hype" aside, I don't get the point. Erlang does not present a shared-memory programming model. Although Erlang can take advantage of multi-core chips, the model for using Erlang on a multi-core node is no different than for using Erlang on a *multi-node* environment with single-core, dual-core, or multi-core nodes.

Also Steve's note about tight coupling of data and code "aka object-orientation" also applies to Erlang -- an Erlang process is essentially such a coupling, and the interface to that process is the message protocol.

I think Steve's argument is right in line with Erlang. His argument goes more against the systems that have one model for intra-process and another for inter-process computing. C and pthreads, Java and its threads, even Haskell and its Software Transactional Memory fall into the category the will suffer according to Steve's argument.

In any case before a "multi-core" chip gets up to 80 cores the on-chip cache and the memory/bus architecture will have to change to something "less shared" anyway. A lot of those transistors will be taking more of a "multi-system-on-a-chip" flavor. All of which will work in Erlang's favor, or at least won't work against Erlang.

Contrary to the original article linked from Steve's, this doesn't, shouldn't, and won't be a NUMA (Non-Uniform Memory Access) architecture, at least not in the way I understand that term. NUMA defines non-uniform access to a *shared* memory, i.e. all the cores can access all the memory as if it were a single, "uniform" memory. Under the covers some memory is closer to one node than to another. Wrong model!

The "multi-system-on-a-chip" architecture will have independent caches, buses, and memories, but not present this as one shared memory. That would be ludicrous. At least to this barely-hardware-literate programmer.

Freescale, nee Motorola, is heading in that direction with multi-core Power chips with per-core backside caches and Power-based system-on-a-chip-like products with a CPU, a graphics processor, and another "media processor".

6 comments:

Anonymous said...

That's the kind of response I like to see--thank you.

Anonymous said...

Steve Dekorte's recent post on "the multi-core wall"

Why go on about shared memory? Amdahl's law is the key. Most Erlang nuthuggers haven't even heard of it, let alone understood the consequences.

Patrick Logan said...

"Amdahl's law is the key. Most Erlang nuthuggers haven't even heard of it, let alone understood the consequences."

Evidence?

Patrick Logan said...

I mean, I'm not doubting the reality of Amdahl's Law. I am wondering what evidence you have the most Erlang nuthuggers haven't even heard of it.

Steve Dekorte said...

I agree that Erlang's non-shared memory model is scallable, though high core MISD machines will run into the memory bottle neck regardless what language they use. A NUMA bus and an Erlang instance per core might overcome some of these issues, but so would running communicating processes written in any language.

Patrick Logan said...

"so would running communicating processes written in any language"

Agreed. Then it becomes a matter of developer efficiency with the various languages and libraries.

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Portland, Oregon, United States
I'm usually writing from my favorite location on the planet, the pacific northwest of the u.s. I write for myself only and unless otherwise specified my posts here should not be taken as representing an official position of my employer. Contact me at my gee mail account, username patrickdlogan.